The i4400 is a low-cost 6U form factor PMC / PrPMC carrier for the VMEbus and forms the basis of a flexible I/O system. It offers the user a means of integrating two single PMC modules or one double PMC module in a VMEbus system. The current version of the i4400 supports PMC modules and also supports Processor PMC modules on one PMC-site. The VME-to-PCI bridge is implemented in an FPGA for flexible VME-to-PCI mapping and to allow future updates and upgrades. The base address of the i4400 is configurable by DIP-switches. The i4400 VME to PCI bridge is mapped in Short I/O (A16) space of the VMEbus. Each PMC site has its own software configurable base address in Standard (A24) or Extended (A32) address space. The DIP-switches are accessible for configuration even when both modules are mounted. The i4400 features flexible rear I/O according to ANSI/VITA 35-2000. All 64 rear I/O signals from PMC site 1 are routed to VME P2. Using optional 5-row VMEbus connectors 46 rear I/O signals from PMC site 2 are routed to VME P2. Using the optional VME64x P0 connector all 64 rear I/O signals from PMC site 2 are available.
As an option the i4400 provides conduction cooling ribs according to ANSI/VITA 20-2001. The interrupt controller on the i4400 has an interrupt vector for each PMC module. If a module is able to generate its own vector, the i4000 simply passes the interrupt request to the VMEbus. Interrupts for each PMC site can be masked separately. The level on which an interrupt is issued to the VMEbus, is software selectable.
The i4400 provides the System Controller Functions like Arbiter, Bus timer and SYSCLK to be used in slot 1 and/or with a PrPMC. On the front of the i4400 is a 7-segment display indicating the boot-status during FPGA boot sequence. Afterwards it can be used by the user for status information.
> VMEbus to PCI-bus interface implemented in FPGA
> Selectable standard VMEbus addressing (A24) with byte
> (Even/odd) or word data transfers (D08(E/O)/D16/D32)
> Features 2 single or 1 double PMC
> 33 MHz/32-bit PCI interface to PMC modules
> 3.3V PCI signaling on PMCs
> Support for one ANSI/VITA 32-2003 compliant Processor PMCs
> Rear I/O on P2 or optional P0 connector
> Available in 3-row and 5-row VME with optional P0
> Software selectable interrupt level
> Thermal sensor for each PMC site
> Front panel status display
> Conduction cooling (optional)